Silicon Based Multijunction Solar Cells
There are a number of SPREE research groups investigating ways to produce high performance multi-junction solar cell that have as their substrate silicon. The use of a silicon substrate can deliver significant cost advantages over current approaches that use Germanium or even III-V compound semiconductor substrates. There are more PV materials beyond silicon with new ones being developed all the time and using them in the most effective way is an important problem. Many of these materials can be integrated with silicon to achieve this end of boosting or turbo-charging silicon solar cells.
A/Prof Stephen Bremner
Due to the limitations placed on photovoltaic power conversion by having a single absorption edge (i.e. the absorbers band gap) the use of multiple materials with different absorption edges has been pursued for decades as a means to exceed single material conversion efficiency limits. The general principle of a MJ solar cell is shown above, left, with the highest energy absorption edge material at the top and the lowest at the bottom, this stacking makes the solar cell an optical filter ensuring the energy of the photons making up the light illuminating the solar cell can be used in the most efficient manner.
Shown above on the right are the results of calculations for the maximum achievable efficiencies for 2 and 3 material stacks. It shows that using the industrially ubiquitous silicon as the bottom cell only slightly reduces the maximum efficiency achievable. These calculations assume we can choose any material we want, but of course in real life there are other factors that limit us somewhat, here is some of the exciting work ongoing at UNSW:
III-V on silicon MJ solar cells via GaP buffers
Working closely with collaborators at the Ohio State University in the US, SPREE researchers, led by A/Prof Stephen Bremner are developing high performance silicon bottom cells that are compatible with the integration of high efficiency III-V solar cells with silicon cells through adaptation of designs developed at UNSW and through novel processes and designs.
The combination of III-V materials with silicon offers the prospect of high efficiency with lower cost substrates than those in current use. The key breakthrough has been the integration of III-V materials with silicon to produce high quality material via deliberately offcut substrates (this is essentially like cutting a loaf of bread at an angle rather than flush). OSU have pioneered the use of a migration enhanced epitaxy (MEE) approach to grow Gallium Phosphide on silicon substrates, with outstanding material quality. SPREE is now working with OSU to develop the silicon bottom cell for these devices. Already this collaboration has yielded a record efficiency device with more to come in the very near future.
SPREE is working on adapting the high efficiency silicon solar cell designs developed at UNSW over many years to be compatible with the processes that take place to allow integration of III-V materials with silicon. Some interesting challenges have arisen with one example being some rather unwelcome effects on the minority carrier lifetimes in silicon (this determine how well your solar cell can ultimately perform). Utilising SPREEs great knowledge of silicon and expertise in processing of silicon these issues have been overcome. With supported through the US Department of Energy Sunshot initiative is working with industry partners to develop high efficiency III-V on silicon solar cells with the potential for commercial development.
There is also work being done to look at making the silicon much thinner than the current thicknesses of 300-350 microns, to drive down material usage even further. This requires more novel silicon device designs, ranging from different materials to passivate the rear surface, to new ways of contacting the silicon with metal for power extraction. With generous financial support from ARENA we are working with collaborators we are looking at approaches, such as HIT (Heterojunction with Intrinsic Thin layer) structures, poly-Si based rear structures. Within SPREE we are looking at adapting a patented room temperature contacting method for the rear of the silicon sub-cell, as well as transition metal oxides for use as carrier selective contacts (CSCs) on the rear of the silicon bottom cell.
Figures: Top left, TEM image of the interface of GaP grown on Si by MOCVD , top right, measured spectral response for PERL type silicon devices showing excellent long wavelength response , ideal for use as bottom cell. Bottom left, evolution of minority carrier lifetime when undergoing thermal treatments, middle, effect of protective layers on the rear of the silicon substrate, right, a lifetime image obtained by photoluminescence imaging, showing the low lifetimes brought by heat treatment and the impact of a protective Mo retaining ring (bright regions) .
 T. Grassman et al, Applied Physics Letters, 102, 142102, 2013.
 C. Yi et al., ‘On the origin of silicon lifetime degradation during anneal in III-V mat4erial growth chambers,” 46th IEEE PVSC, Chicago, 2019.
Figures directly above taken from  I. Almansouri et al., IEEE Journal of Photovoltaics, 5(2), 683-690, 2014,  I. Almansouri et al., IEEE Journal of Photovoltaics, 5(3), 968-976, 2015
Find out more about the Academic Staff Working on this Project and how to join the research team